Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

A complementary metal-oxide semiconductor (CMOS) device, comprising:

• an n-channel metal-oxide semiconductor (NMOS) transistor comprising:
• an NMOS active channel pattern including a plurality of NMOS thin body channels stacked vertically and at least one tunnel interposed between the NMOS thin body channels formed on a first region of a semiconductor substrate;
• an NMOS insulating layer surrounding a surface of the NMOS thin body channel;
• and
• an NMOS metal gate filling the tunnel and surrounding the NMOS insulating layer;
• and
• a p-channel metal-oxide semiconductor (PMOS) transistor comprising:
• a PMOS active channel pattern including a plurality of PMOS thin body channels stacked vertically and at least one tunnel interposed between the PMOS thin body channels formed on a second region of the semiconductor substrate;
• a PMOS insulating layer surrounding a surface of the PMOS thin body channel;
• and
• a PMOS metal gate filling the tunnel and surrounding the PMOS insulating layer;
• wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.

A method of manufacturing a complementary metal-oxide semiconductor (CMOS) device, comprising:

• forming a preliminary layer for forming a channel on a semiconductor substrate in which an NMOS region and a PMOS region are defined, the preliminary layer including a sacrificial layer and a thin body channel layer;
• patterning the preliminary layer for forming the channel to form a preliminary pattern for forming an NMOS channel in the NMOS region and a preliminary pattern for forming a PMOS channel in the PMOS region;
• anisotropically etching the ends of the preliminary patterns for forming the NMOS and PMOS channels until a surface of the semiconductor substrate is exposed to form a groove, thereby forming a pattern for forming the NMOS channel in the NMOS region and a pattern for forming the PMOS channel in the PMOS region;
• forming an NMOS source/drain region and a PMOS source/drain region by filling the groove with a material layer;
• forming an NMOS thin body channel and a PMOS thin body channel by removing a residual sacrificial layer of the patterns for forming the NMOS and PMOS thin body channels;
• forming an NMOS insulating layer surrounding the NMOS thin body channel on a surface of the NMOS thin body channel when the PMOS region is masked;
• forming an NMOS metal gate pattern on a surface of and surrounding the NMOS insulating layer;
• forming a PMOS insulating layer surrounding the PMOS thin body channel on a surface of the PMOS thin body channel when the NMOS region is masked;
• and
• forming a PMOS metal gate pattern on a surface of and surrounding the PMOS insulating layer;
• wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.

A method of manufacturing a complementary metal-oxide semiconductor (CMOS) device, comprising:

• forming a preliminary layer for forming a channel on a semiconductor substrate in which an NMOS region and a PMOS region are defined, the preliminary layer including a sacrificial layer and a thin body channel layer;
• forming a first mask pattern defining an active region on the preliminary layer for forming a channel;
• etching the preliminary layer for forming the channel using the first mask pattern as an etch mask to form a preliminary pattern for forming an NMOS channel in the NMOS region and a preliminary pattern for forming a PMOS channel in the PMOS region;
• forming a second mask pattern on the preliminary patterns for forming NMOS and PMOS channels to expose both ends of the preliminary patterns for forming NMOS and PMOS channels and to define a channel region;
• anisotropically etching the preliminary patterns for forming the NMOS and PMOS channels until a surface of the semiconductor substrate is exposed using the second mask pattern as an etch mask to form a groove, thereby forming a pattern for forming the NMOS channel in the NMOS region and a pattern for forming the PMOS channel in the PMOS region;
• forming an NMOS source/drain region and a PMOS source/drain region by filling the groove with a material layer;
• forming a third mask pattern covering the NMOS and PMOS source/drain regions and exposing an upper surface of the pattern for forming the NMOS and PMOS channels;
• forming a fourth mask pattern covering the PMOS region;
• exposing a side of the pattern for forming the NMOS channel using the third mask pattern of the NMOS region as an etch mask;
• selectively removing a residual sacrificial layer of the pattern for forming the NMOS channel to form an NMOS thin body channel;
• forming an NMOS insulating layer on a surface of and surrounding the NMOS thin body channel;
• forming an NMOS metal gate pattern on and surrounding the NMOS insulating layer;
• removing the fourth mask pattern;
• forming a fifth mask pattern covering the NMOS region;
• exposing a side of the pattern for forming the PMOS channel using the third mask pattern of the PMOS region as an etch mask;
• selectively removing a residual sacrificial layer of the pattern for forming the PMOS channel to form a PMOS thin body channel;
• forming a PMOS insulating layer on a surface of and surrounding the PMOS thin body channel;
• forming a PMOS metal gate pattern on and surrounding the PMOS insulating layer;
• and
• removing the fifth mask pattern;
• wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.