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US 2006/0125017 A1Published application
Stacked memory cell utilizing negative differential resistance devices
AssigneeSynopsys, Inc.
InventorTsu-Jae Liu
Life of this patent
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Abstract
A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell.
Claims19
A memory cell comprising:
- a first negative differential resistance field effect transistor (NDR-FET);
- a second NDR-FET connected in series with the first NDR-FET;
- and
- an access transistor connected between a data line and a junction between the first NDR-FET and the second NDR-FET,
- wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.
2 more elements
A method for making a memory cell, the method comprising:
- forming a first negative differential resistance (NDR) field effect transistor (FET) in series with a second NDR-FET;
- forming an access transistor for connecting a data line to a junction between the first NDR-FET and the second NDR-FET,
- wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.
Dependencies are inferred from the claim text.