Varactor
AssigneeHoneywell International Inc.
InventorMohammed Fathimulla
Life of this patent
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Abstract
A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of the depletion mode transistor and the enhancement mode transistor are coupled together, and the drains of the depletion mode transistor and the enhancement mode transistor are coupled together. The enhancement mode transistor has a p/n junction. A bias source is coupled to the gates and the sources and drains so as to control the capacitance.
Claims39
A varactor having a capacitance comprising:
- a depletion mode transistor having a gate, a source, and a drain;
- an enhancement mode transistor having a gate, a source, and a drain, wherein the gates of the depletion mode transistor and the enhancement mode transistor are coupled together, wherein the sources and drains of the depletion mode transistor and the enhancement mode transistor are coupled together, and wherein the enhancement mode transistor has a p/n junction;
- and,
- a bias source coupled to the gates and the sources and drains so as to control the capacitance.
A method of determining temperature comprising:
- detecting a leakage current through a p/n diode formed by a body region and a source region of a transistor, wherein the transistor includes a gate and a drain region, and wherein the body region separates the source and drain regions;
- and,
- converting the leakage current to temperature.
A varactor having a capacitance comprising:
- a gate;
- a source;
- a drain;
- and,
- a body tie forming a p/n junction with the source, wherein the p/n junction comprises the capacitance of the varactor.
A varactor comprising:
- a depletion mode transistor;
- an enhancement mode transistor;
- and,
- a bias source coupled to both the depletion mode transistor and the enhancement mode transistor and arranged to control the depletion mode transistor and the enhancement mode transistor so as to control a capacitance of the varactor.
A power transistor comprising:
- a depletion mode transistor having a gate, a source, and a drain;
- and,
- an enhancement mode transistor having a gate, a source, and a drain, wherein the gates of the depletion mode transistor and the enhancement mode transistor are coupled together, wherein the sources of the depletion mode transistor and the enhancement mode transistor are coupled together, and wherein the drains of the depletion mode transistor and the enhancement mode transistor are coupled together.
Dependencies are inferred from the claim text.