US 2006/0125008 A1 · DUAL STRESSED SOI SUBSTRATES

Abstract

The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

Claims30

Dependent claims

A method of fabricating a substrate comprising the steps of:

forming a compressive dielectric layer on a first portion of a substrate;
forming a tensile dielectric layer on a second portion of a substrate;
forming a semiconducting layer atop said compressive dielectric layer and said tensile dielectric layer;
and
forming an isolation region through said semiconducting layer and separating said tensile dielectric layer from said compressive dielectric layer, wherein said compressive dielectric layer transfers a tensile stress to a portion of said semiconducting layer overlying said compressive dielectric layer and said tensile dielectric layer transfers a compressive stress to a portion of said semiconducting layer overlying said tensile dielectric layer.

2 more elements

A method of forming a substrate comprising:providing an initial structure comprising a Si-containing substrate having a tensile dielectric positioned on a first surface of said Si-containing substrate and a compressive dielectric positioned on a second surface of said Si-containing substrate, said tensile dielectric and said compressive dielectric separated by an insulating material;

removing said insulating material to expose a portion of said Si-containing ubstrate between said first surface and said second surface of said Si-containing substrate;
recessing said Si-containing substrate from said first and said second surface of said Si-containing substrate to provide recessed portions of said Si-containing substrate adjacent said first surface of said substrate and said second surface of said substrate;
forming an oxide positioned on recessed portions of said Si-containing substrate, said oxide being coplanar to an upper surface of said compressive layer and said tensile layer to provide a planar top surface;
bonding a wafer to said planar top surface;
implanting said Si-containing substrate to provide a damaged interface;
separating said Si-containing substrate about said damaged interface, wherein a damaged surface of said Si-containing substrate remains;
planarizing said damaged surface of said Si-containing substrate stopping on a surface of said oxide on said recessed portions of said Si-containing substrate, wherein planarizing said Si-containing substrate to said oxide produces a semiconducting layer atop said tensile material and said compressive material;
and
removing said oxide, wherein said tensile dielectric transfers a compressive stress to said semiconducting layer and said compressive dielectric transfers a tensile stress to said semiconducting layer.

6 more elements

Dependencies are inferred from the claim text.

Dual stressed soi substrates

Life of this patent

Dual stressed soi substrates

Life of this patent

Abstract

Claims30