Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same

A semiconductor device having an N-channel field effect transistor, wherein the N-channel field effect transistor includes

• a substrate,
• a high dielectric constant gate insulating film formed on the substrate,
• a gate electrode formed on the high dielectric constant gate insulating film,
• an extension region formed on both sides of the gate electrode in the substrate and containing at least one of arsenic (As) and phosphorus (P) as N-type impurities, and
• a pocket region formed under the extension region in the substrate and containing P-type impurities, and
• provided that X1 indicates a thickness (nm) of the high dielectric constant gate insulating film and Y1 indicates an amount of As (/cm2) that is contained in the extension region as the N-type impurities, Y1 is in the following range with respect to X1:
• Y1≦−2.5×1014·X1+1.5×1015.

A semiconductor device having an N-channel field effect transistor, wherein the N-channel field effect transistor includes

• a substrate,
• a high dielectric constant gate insulating film formed on the substrate,
• a gate electrode formed on the high dielectric constant gate insulating film,
• an extension region formed on both sides of the gate electrode in the substrate and containing arsenic (As) and phosphorus (P) as N-type impurities, and
• a pocket region formed under the extension region in the substrate and containing P-type impurities, wherein
• the extension region contains a larger amount of P than that of As.

A method for manufacturing a semiconductor device having a P-channel field effect transistor, wherein the P-channel field effect transistor is formed by a process including the steps of

• forming a high dielectric constant gate insulating film on a substrate,
• forming a gate electrode on the high dielectric constant gate insulating film,
• forming an extension region by introducing P-type impurities into the substrate by using at least the gate electrode as a mask, and
• forming a pocket region by introducing N-type impurities under the extension region in the substrate by using at least the gate electrode as a mask, wherein
• an amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

A semiconductor device having a P-channel field effect transistor, wherein the P-channel field effect transistor includes

• a substrate,
• a high dielectric constant gate insulating film formed on the substrate,
• a gate electrode formed on the high dielectric constant gate insulating film,
• an extension region formed on both sides of the gate electrode in the substrate and containing P-type impurities, and
• a pocket region formed under the extension region in the substrate and containing at least one of arsenic (As) and phosphorus (P) as N-type impurities, and
• provided that X2 indicates a thickness (nm) of the high dielectric constant gate insulating film and Y2 indicates an amount of As (/cm2) that is contained in the pocket region as the N-type impurities, Y2 is in the following range with respect to X2:
• Y2≦−1.5×1013·X2+9.0×1013.

A semiconductor device having a P-channel field effect transistor, wherein the P-channel field effect transistor includes

• a substrate,
• a high dielectric constant gate insulating film formed on the substrate,
• a gate electrode formed on the high dielectric constant gate insulating film,
• an extension region formed on both sides of the gate electrode in the substrate and containing P-type impurities, and
• a pocket region formed under the extension region in the substrate and containing arsenic (As) and phosphorus (P) as N-type impurities, wherein
• the pocket region contains a larger amount of P than that of As.