NROM memory cell, memory array, related devices and methods

A method for multistate dynamic random access memory (DRAM) operation, the method comprising:

• writing to a plurality of vertical transistors arranged in an array of rows and columns and extending outwardly from a substrate, adjacent transistors separated by trenches, wherein each transistor in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the DRAM array includes a source line formed in the bottom of the trenches between rows of the vertical transistors and coupled to the source regions of each transistor along rows of the vertical transistors, and wherein the DRAM array includes a number of bit lines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical transistors in the reverse direction includes:
• biasing a source line for two column adjacent vertical transistors sharing a trench to a voltage higher than VDD;
• grounding a bit line coupled to one of the drain regions of the two column adjacent vertical transistors in the vertical transistor to be programmed;
• applying a gate potential to the gate for each of the two column adjacent vertical transistors to create a hot electron injection into the gate insulator of the vertical transistor to be programmed adjacent to the source region such that the addressed transistors become programmed transistors that operate at reduced drain source current in a forward direction;
• reading one or more vertical transistors in the DRAM array in a forward direction, wherein reading the one or more transistors in the forward direction includes;
• grounding a source line for two column vertical transistors sharing a trench;
• precharging the drain regions of the two column adjacent vertical transistors sharing a trench to a fractional voltage of VDD;
• and
• applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical transistors sharing a trench such that a conductivity state of an addressed vertical transistor can be compared to a conductivity state of a reference cell.

A method for multistate dynamic random access memory (DRAM) operation in a DRAM device comprising a memory array having a plurality of transistors arranged in an array of rows and columns and extending outwardly from a substrate, adjacent transistors separated by trenches, wherein each transistor in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the DRAM array includes a source line formed in the bottom of the trenches between rows of the vertical transistors and coupled to the source regions of each transistor along rows of the vertical transistors, and wherein the DRAM array includes a number of bit lines coupled to the drain region along rows in the DRAM array, the method comprising:

• writing to a vertical transistor in the reverse direction by biasing a source line for two column adjacent vertical transistors sharing a trench to a voltage higher than VDD, grounding a bit line coupled to one of the drain regions of the two column adjacent vertical transistors in the vertical transistor to be programmed and applying a gate potential to the gate for the two column adjacent vertical transistors to create a hot electron injection into the gate insulator of the vertical transistor to be programmed adjacent to the source region such that the addressed transistor becomes a programmed transistor that operates at reduced drain source current in a forward direction;
• and
• reading the programmed transistor in a forward direction by grounding the source line for two column vertical transistors sharing the trench, precharging the drain regions of the two column adjacent vertical transistors sharing the trench to a fractional voltage of VDD, and applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical transistors sharing the trench such that a conductivity state of the addressed vertical transistor can be compared to a conductivity state of a reference cell.