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US 2006/0124986 A1Published application
CMOS image sensor and manufacturing method thereof
AssigneeDongbu Electronics Co., Ltd.
InventorSang-Gi Lee
Life of this patent
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Abstract
A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.
Claims11
A method for manufacturing a CMOS image sensor, comprising:
- forming a dummy gate stack with a gate insulation layer and a dummy gate electrode layer on a semiconductor substrate;
- forming a gate spacer layer on at least a sidewall of the dummy gate stack;
- forming a source/drain region on the semiconductor substrate by an ion implantation process using the dummy gate stack and the gate spacer layer as an implantation mask;
- removing the dummy gate stack to expose a partial surface of the semiconductor substrate;
- forming an insulation layer with a high dielectric constant on the exposed surface of the semiconductor substrate;
- forming a gate electrode layer on the insulation layer with a high dielectric constant;
- sequentially forming a liner layer and a dummy pre-metal dielectric layer on the entire surface of the semiconductor substrate having the gate electrode layer thereon;
- partially removing the dummy pre-metal dielectric layer and the liner layer to expose a surface of the gate electrode by a planarization process;
- sequentially removing the dummy pre-metal dielectric layer and the liner layer in a peripheral circuit region by using a mask layer pattern to cover a pixel region;
- forming a silicide layer on the gate electrode layer in the pixel region and on the gate electrode layer and the source/drain region in the peripheral circuit region by a silicidation process;
- and
- removing the dummy pre-metal dielectric layer and the liner layer remaining in the pixel region.
9 more elements
A CMOS image sensor comprising:
- a semiconductor substrate;
- gate spacers formed on the semidonductor substrate;
- a gate insulation layer with a high dielectric constant formed between the gate spacers and on the semiconductor substrate after removing a dummy gate stack formed between the gate spacers;
- a gate electrode formed between the gate spacers and on the gate insulation layer with a high dielectric constant;
- a silicide layer formed on the gate electrode;
- and
- a source/drain region formed in the semiconductor substrate at a position exterior to the gate.
4 more elements
Dependencies are inferred from the claim text.