DRAM technology compatible processor/memory chips

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of outputs;
• and
• a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being operably coupled to receive the outputs of the first logic plane and interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,
• wherein at least one of the non-volatile memory cells includes:
• a transistor;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system, comprising:

• an electronic device;
• and
• a processor operatively coupled to the electronic device;
• and
• wherein the processor includes at least one programmable logic array including:
• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and
• wherein the non-volatile memory cells of the first logic plane each include:
• a metal oxide semiconductor field effect transistor;
• a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs;
• and
• a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to the gate of the transistor.

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs;
• and
• a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric;
• and
• an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs;
• and
• a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor;
• a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric;
• and
• an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells that are interconnected to provide a number of logic outputs;
• and
• a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;
• a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system with a programmable logic array, comprising:

• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic output;
• and
• a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide, the gate oxide being adapted to act as a tunneling oxide;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the die includes at least one programmable logic array including:
• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile first memory cells arranged in rows and columns that are interconnected to provide a number of first logic outputs;
• and
• a second logic plane having a number of non-volatile second memory cells arranged in rows and columns, the non-volatile second memory cells being adapted to receive the outputs of the first logic plane and that are interconnected to produce a number of second logic outputs,
• wherein the first non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs, and
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide, wherein the gate oxide has a thickness of less than 100 angstroms;
• a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the MOSFET.