Structure and method to generate local mechanical gate stress for mosfet channel mobility modification

A method of forming a semiconductor structure having a local mechanical gate stress comprising the steps of:

• providing a semiconductor structure having layers of a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a hard mask located on a surface of a semiconductor substrate, said semiconductor substrate containing a trench isolation region;
• patterning said layers to provide at least one patterned gate stack for a NFET and a least one patterned gate stack for a PFET, said NFET and PFET are separated by said trench isolation region;
• forming at least one spacer on sidewalls of each patterned gate stack and forming silicided source/drain regions in said semiconductor substrate adjacent each patterned gate stack;
• forming a planarized dielectric film that exposes a top surface of each patterned gate stack;
• selectively forming a silicide or a tensile metal in said at least one patterned gate stack for said PFET;
• and selectively forming a compressive metal in said at least one patterned gate stack for said NFET.

A method of forming a semiconductor structure having a local mechanical gate stress comprising the steps of:

• providing a semiconductor structure having layers of a gate dielectric, a first gate electrode layer, a barrier layer, a second gate electrode layer and a hard mask located on a surface of a semiconductor substrate, said semiconductor substrate containing a trench isolation region and said second gate electrode layer comprising a tensile metal or a silicide;
• patterning said layers to provide at least one patterned gate stack for a NFET and a least one patterned gate stack for a PFET, said NFET and PFET are separated by said trench isolation region;
• forming at least one spacer on sidewalls of each patterned gate stack and forming silicided source/drain regions in said semiconductor substrate adjacent each patterned gate stack;
• forming a planarized dielectric film that exposes a top surface of each patterned gate stack;
• and
• selectively forming a compressive metal in said at least one patterned gate stack for said NFET.