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US 2006/0124969 A1Published application
MOS transistor and manufacturing method thereof
AssigneeDongbuAnam Semiconductor Inc.
InventorDong-Il Byun
Life of this patent
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Abstract
A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.
Claims16
A MOS transistor, comprising:
- a gate insulation layer and a gate electrode layer sequentially formed on a channel region of a semiconductor substrate;
- a gate spacer layer formed on a sidewall of the gate electrode layer and the gate insulation layer;
- an extended source/drain region formed in the semiconductor substrate and having a predetermined depth, the extended source/drain region being defined by the sidewall of the gate electrode layer;
- a first source/drain region that is deeper than the extended source/drain region and that is formed in the semiconductor substrate contacting the extended source/drain region, the first source/drain region being defined by the gate spacer layer;
- and
- a second source/drain region that is shallower than the extended source/drain region and that is formed in the first source/drain region contacting the extended source/drain region, the second source/drain region being defined by the gate spacer layer.
3 more elements
A manufacturing method of a MOS transistor, comprising:
- forming a gate stack with a gate insulation layer and a gate electrode layer on a semiconductor substrate;
- forming an extended source/drain region having a predetermined depth by a first ion implantation process using the gate stack as an ion implantation mask;
- forming a gate spacer layer on a sidewall of the gate stack;
- forming a first source/drain region that is deeper than the extended source/drain region by a second ion implantation process using the gate spacer layer as an ion implantation mask;
- and
- forming a second source/drain region that is shallower than the extended source/drain region by a third ion implantation process using the gate spacer layer as an ion implantation mask.
3 more elements
Dependencies are inferred from the claim text.