CMOS inverter constructions
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
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Abstract
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).
Claims12
1-19. (canceled)
The inverter construction of claim 22 wherein the electrical interconnect comprises n-type doped semiconductive material which extends from said one of the NFET device source/drain regions to the third layer.
(canceled)
A CMOS inverter construction comprising:
- a substrate;
- a first layer over the substrate;
- the first layer comprising p-type doped Si/Ge and having a relaxed crystalline lattice;
- a second layer over the first layer:
- the second layer comprising p-type doped Si/Ge and having a strained crystalline lattice;
- an NFET device over the second layer and having a transistor gate, the NFET device including n-type doped source/drain regions extending downwardly from adjacent the gate and into the first and second layers
- a third layer over the transistor gate;
- the third layer comprising n-type doped Si/Ge;
- a fourth layer over the third layer;
- the fourth layer comprising n-type doped silicon;
- a PFET device over the NFET device and sharing the transistor gate with the NFET device;
- the PFET device including p-type doped source/drain regions extending upwardly from adjacent the gate and into the third layer;
- an electrical interconnect which electrically connects the third layer to one of the NFET device source/drain regions;
- wherein the substrate comprises p-type doped monocrystalline silicon;
- and
- wherein the first layer extends into and physically contacts the p-type doped monocrystalline silicon of the substrate.
24-61. (canceled)
Dependencies are inferred from the claim text.