US 2006/0124582 A1Published application

Method for fabricating bottom electrodes of stacked capacitor memory cells and method for cleaning and drying a semiconductor wafer

AssigneeInfineon Technologies AG

InventorSrivatsa Kundalgurki

Life of this patent

Estimating the term…

Loading patent…

Abstract

Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which leads to a electrical conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layer, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.

Claims22

Dependent claims

A method for fabricating bottom electrodes of stacked capacitor memory cells, comprising:

providing a semiconductor wafer having a substrate;
forming a plurality of contact plugs on the surface of the substrate;
depositing a first sacrificial conductive layer on the surface of the substrate and the plurality of contact plugs;
depositing a mask layer on the first sacrificial conductive layer;
etching a plurality of trenches into the mask layer, each of the trenches being located above the contact plugs and ranging from the surface of the mask layer to the contact plugs;
removing the first sacrificial conductive layer above the contact plugs;
depositing a second metal layer on the surface of the mask layer, the second metal layer covering the side walls of the trench and the contact plugs;
removing the mask layer by wet etching;
providing a wafer dryer, the wafer dryer comprising a basin filled with a cleaning liquid for rinsing the wafer and a drying area above the surface of the cleaning liquid;
providing a voltage source having a first terminal and a second terminal;
providing a counter electrode, the counter electrode being electrically connected to the first terminal;
electrically connecting the second terminal of the voltage source to the first sacrificial conductive layer and second metal layer;
immersing the wafer and the counter electrode into the cleaning liquid of the basin;
selecting an output voltage of the voltage source;
gradually withdrawing the wafer from the basin into the drying area;
and
removing the first sacrificial conductive layer by dry etching the first metal layer selectively to the second metal layer to form electrically isolated elements of the second metal layer serving as bottom electrodes.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/011,038Filed 15 Dec 2004
Published: 15 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10P 70/27
Cleaning during device manufacture: during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10D 1/716
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor