High speed filter
AssigneeESS Technology, Inc.
InventorAndrew Mallinson
Life of this patent
Estimating the term…
Abstract
An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.
Claims31
A circuit for correlating an input signal comprising:
- a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit for sampling the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a predetermined scaling factor;
- a timing circuit for causing said timing signal to be presented in time-delayed succession to successive ones of said processing elements;
- and,
- means for summing the scaled output of said processing elements.
The method of correlating an input signal to an apparent reference signal, comprising:
- generating a series of phase shifted analog samples of the input signal;
- scaling successive ones of said samples by coefficient values representing the reference signal;
- and,
- summing said scaled samples.
A circuit for correlating an input signal with a desired frequency response, comprising:
- a first and a second arrays of parallel processing elements, each of said processing elements comprising an analog sampling circuit for sampling the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a predetermined scaling factor;
- a timing circuit for causing said timing signal to be presented in time-delayed succession to successive parallel pairs of said processing elements;
- a summer for summing the scaled output of said processing elements comprising said first array;
- and,
- a summer for summing the scaled output of said processing elements comprising said second array.
The method of correlating an input signal to an apparent reference signal, comprising:
- generating a series of phase shifted analog samples of the input signal;
- scaling successive ones of said samples by coefficient values representing the normal component of said reference signal;
- scaling successive ones of said samples by coefficient values representing the quadrature component of said reference signal;
- summing said normal scaled samples;
- summing said quadrature scaled samples;
- and,
- deriving the root mean square of said normal and quadrature sums.
The method of 14 wherein said step of generating a series of phase shifted analog samples comprises providing phase shifted timing signals to a plurality of analog sample and hold circuits.
A circuit for correlating an input signal comprising:
- a parallel array of processing elements, each of said processing elements comprising a comparator for comparing said input signal with a predetermined reference value in response to a timing signal and outputting a value of +1 or −1;
- a timing circuit for causing said timing signal to be presented in time-delayed succession to successive ones of said processing elements;
- a multiplier for scaling the output of said comparator with a predetermined scaling factor representative of a normal or quadrature sine wave;
- and,
- a summer for summing the scaled output of said processing elements.
A circuit for correlating an input signal with an apparent reference signal wherein the apparent reference signal is embedded in an array of analog sampling circuits by means of scaling factors representative of the characteristics of said reference signal, and wherein the sampling point for the input signal advances through successive sampling circuits.
A circuit for correlating an input signal comprising:
- an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produced a scaled signal;
- a timing circuit for causing the scaled signal to be presented in time-delayed succession to successive sampled of the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample, and;
- a multiplier configured to multiply the scaled signal and produce an output.
Dependencies are inferred from the claim text.