Digital frequency difference detector with inherent low pass filtering and lock detection

A digital frequency difference detector, comprising:

• a first frequency detection input for receiving a first signal;
• a second frequency detection input for receiving a second signal;
• an n-bit counter for counting pulses received at said first frequency-detection input, whereby said n-bit counter maintains a pulse-count of said first signal;
• an m-bit counter for counting pulses received at said second frequency detection input, whereby said m-bit counter maintains a pulse-count of said second signal, and wherein m is greater than n;
• a first memory cell for storing a SET condition in response to the nth bit within said m-bit counter transitioning into a first logic state and for maintaining said SET condition irrespective of said nth bit within said m-bit counter transitioning out of said first logic state;
• a second memory cell for storing a SET condition in response to the (n+1)th bit within said m-bit counter transitioning into said first logic state and for maintaining said SET condition irrespective of said (n+1)th bit transitioning out of said first logic state;
• wherein said n-bit counter and said m-bit counter are halted in response to the nth bit within said n-bit counter transitioning into said first logic state;
• and
• wherein upon said halting of said n-bit and m-bit counters, said digital frequency difference detector determines:
• a) that the frequency of said second signal is lower than said first signal if neither of said first or second memory cells have said SET condition stored;
• or
• b) that the frequency of said second signal is higher than said first signal if said second memory cell has said SET condition stored;
• or
• c) that the frequency of said second signal is higher than said first signal if said first memory cell has said SET condition stored and any bit within said m-bit counter excluding a predetermined number of least significant bits is set to said first logic state;
• or
• d) that the frequency of said second signal is locked to said first signal if said first memory cell has said SET condition stored and said second memory cell does not have said SET condition stored and no bit within said m-bit counter excluding said predetermined number of least significant bits is set to said first logic state.

A method for detecting a frequency difference between a first signal and a second signal, said method comprising:

• monitoring said first signal to count pulses in said first signal up to a first predetermined value;
• monitoring said second signal to count pulses in said second signal;
• when the pulse count of said first signal reaches said predetermined value, comparing said predetermined value with the current pulse count of said second signal, and determining:
• a) that the frequency of the second signal is lower than the frequency of the first signal if the predetermined value is greater than the pulse count of the second signal by an amount greater than a predefined margin;
• or
• b) that the frequency of the second signal is greater than the frequency of the first signal if the predetermined value is less than the pulse count of the second signal by an amount greater than said predefined margin;
• and
• c) that the frequency of the second signal is locked to the frequency of the first signal if the magnitude of the difference between the predefined value and the pulse count of the second signal is within said predefined margin.