# US 2006/0109352 A1 · Method and apparatus for in a multi-pixel pick-up element reducing a pixel-based resolution and/or effecting anti-aliasing through selectively combining selective primary pixel outputs to combined secondary pixel outputs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0109352 A1 - Document ID: US20060109352A1 - Status: Published application - Kind: A1 - Application number: 10/994,227 - Filed: 2004-11-23 - Published: 2006-05-25 - Earliest claimed: 2004-11-23 - Assignees: Dalsa, Inc. - Inventors: Cornelis Draijer - Web page: https://patentgrep.com/patent/US20060109352A1 ## CPC - H04N 25/46: by combining or binning pixels - H04N 23/84: for processing colour signals - H04N 25/70: SSIS architectures; Circuits associated therewith - H04N 25/713: Transfer or readout registers; Split readout registers or multiple readout registers - H04N 25/73: using interline transfer [IT] - H04N 25/134: {based on three different wavelength filter elements} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A method for in a multi-pixel pick-up element reducing a pixel-based resolution and/or effecting anti-aliasing through selectively combining selective primary pixel outputs to combined secondary pixel outputs, comprises the following steps: row-wise, whether or not restrictively, selecting pixels for loading into a first parallel-in register; serial shifting of the load within the register for aligning selected first pixels in the first parallel-in register with selected second pixels not in the first parallel-in register; arithmetically combining pixel groups so aligned; and outputting combination results from preselected multi-pixel configurations as secondary pixels. The invention is applicable to a selection from amongst a two-dimensional pick-up array, an Interline Architecture, a Frame Transfer Architecture, a combination of those two, a TDI pick-up array, and a linear pick-up array, and for both mono-color and multi-color pick-up facilities. ## Claims ### Claim 1 A method for reducing a pixel-based resolution in a multi-color pick-up element through selectively combining primary pixel outputs to combined secondary pixel outputs, said method comprising the following steps: selecting pixels of one row for loading these pixels into a first parallel-in register; serial shifting of the load within said register for aligning color pixels in said first parallel-in register with selected like-colored pixels not in said first parallel-in register; arithmetically combining the pixel contents with the pixel groups so aligned; and outputting combination results as said secondary pixels. ### Claim 2 A method for effecting anti-aliasing in a one-color pick-up element through selectively combining primary pixel outputs to combined secondary pixel outputs, through effecting the following steps: selecting pixels of one row for loading these pixels in a first parallel-in register; serial shifting of the load within said register for aligning selected first pixels in said first parallel-in register with selected second pixels not in said first parallel-in register; arithmetically combining the pixel contents with the pixel groups so aligned; and outputting combination results from preselected multi-pixel configurations as said secondary pixels. ### Claim 3 (depends on 1) A method as claimed in claim 1, wherein said arithmetically combining is executed between said first parallel-in register and a second parallel-in register. ### Claim 4 (depends on 1) A method as claimed in claim 1, as applied on a selection from amongst a two-dimensional pick-up array, an Interline Architecture, a Frame Transfer Architecture, a combination of those two, a TDI pick-up array, and a linear pick-up array. ### Claim 5 (depends on 1) A method as claimed in claim 1, whilst using said serial shifting in both forward and backward directions. ### Claim 6 (depends on 1) A method as claimed in claim 1, whilst allowing for both reading-out and dumping of selected pixel and/or combined pixel data. ### Claim 7 (depends on 1) A method as claimed in claim 1, which allows for faster read-out through data reduction. ### Claim 8 (depends on 1) A method as claimed in claim 1, wherein outputted data allow for immediate gamma correction and subsequent transfer to an image representation facility (screen or display). ### Claim 9 (depends on 1) A method as claimed in claim 1 for use in anti-aliasing through binning of overlapping data sampling. ### Claim 10 (depends on 1) An apparatus being arranged for implementing a method as claimed in claim 1 and comprising a multi-color pick-up element feeding a reducing facility for reducing a pixel-based resolution through selectively combining selective primary pixel outputs to combined secondary pixel outputs, for presenting thereof on an output for subsequent usage, said apparatus comprising the following: a selection facility for row-wise selecting pixels for loading these pixels into a first parallel-in register; shift control means for serial shifting of the load within said first parallel-in register for aligning color pixels in said first parallel-in register with selected like-colored pixels not in said first parallel-in register; arithmetic combination means fed by said first parallel-in register for arithmetically combining pixel groups so aligned; and output means fed by said combining means for outputting combination results as said secondary pixels. ### Claim 11 (depends on 2) An apparatus being arranged for implementing a method as claimed in claim 2 for effecting anti-aliasing through selectively combining selective primary pixel outputs to combined secondary pixel outputs, said apparatus comprising: selecting means for row-wise selecting pixels for loading these pixels into a first parallel-in register; shift control means for serially shifting the load within said register for aligning selected first pixels in said first parallel-in register with selected second pixels not in said first parallel-in register; combining means fed by said first parallel-in register for arithmetically combining pixel groups so aligned; and output means fed by said combining means for outputting combination results from preselected multi-pixel configurations as said secondary pixels. ### Claim 12 (depends on 10) A digital electronic camera provided with an apparatus as claimed in claims 10. ### Claim 13 (depends on 11) A digital electronic camera provided with an apparatus as claimed in claims 11. ### Claim 14 (depends on 2) A method as claimed in claim 2, wherein said arithmetically combining is executed between said first parallel-in register and a second parallel-in register. ### Claim 15 (depends on 2) A method as claimed in claim 2, as applied on a selection from amongst a two-dimensional pick-up array, an Interline Architecture, a Frame Transfer Architecture, a combination of those two, a TDI pick-up array, and a linear pick-up array. ### Claim 16 (depends on 2) A method as claimed in claim 2, whilst using said serial shifting in both forward and backward directions. ### Claim 17 (depends on 2) A method as claimed in claim 2 for use in anti-aliasing through binning of overlapping data sampling.