Automatic addition of power connections to chip power

A computer program product comprising a computer usable medium having a computer readable program for designing a hierarchical, multi-layer integrated circuit (IC) chip design having a plurality of hierarchical levels of said multi-layer IC design ordered from a lower to a higher level, wherein a lower hierarchical level comprises a subset of the next higher-level, said computer readable program embodied in said medium, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

• providing a first multi-layer design corresponding to a first hierarchical level, said first multi-layer design formed according to a first design stage corresponding to said first hierarchical level, wherein said first multi-layer design comprises circuit features occupying areas of said first hierarchical level, wherein said providing includes providing details of said circuit features occupying areas of layers of said first multi-layer design;
• in a higher level design stage corresponding to a hierarchical level higher than said first level, determining free areas of said first multi-layer design which are not yet occupied by circuit features;
• and
• performing further design processing of said free areas of said first multi-layer design within said higher level design stage.