Method for circuit sensitivity driven parasitic extraction
AssigneeTexas Instruments Incorporated
InventorsUsha Narasimha, Anthony Hill, Nagaraj Savithri
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AssigneeTexas Instruments Incorporated
InventorsUsha Narasimha, Anthony Hill, Nagaraj Savithri
Estimating the term…
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each mode from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.
A method for determining timing of an integrated circuit design comprising the steps of:
Dependencies are inferred from the claim text.