Method of screening ASIC defects using independent component analysis of quiescent current measurements
AssigneeLSI Logic Corporation
InventorsRitesh Turakhia, Robert Benware
Life of this patent
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AssigneeLSI Logic Corporation
InventorsRitesh Turakhia, Robert Benware
Estimating the term…
A method and computer program for screening defects in integrated circuit die includes steps of: (a) receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die; (b) generating a test matrix from the quiescent current measurements for each die in the sample lot; (c) computing a de-mixing matrix from independent component analysis that models passing die in the sample lot; (d) generating a matrix of sources as a product of the test matrix and the de-mixing matrix; (e) normalizing the matrix of sources to zero mean and unit variance; (f) selecting a statistical limit of the passing die in the sample lot to determine a maximum and a minimum quiescent current limit for each of the sources; and (g) generating as output the maximum and the minimum quiescent current limit for each of the sources.
A method comprising steps of:
A method comprising steps of:
A computer program product comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:
A computer program product comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:
Dependencies are inferred from the claim text.