High speed energy conserving scan architecture

A system-on-chip (“SoC”), comprising:

• a series of flip-flops, at least some of the flip-flops comprising:
• a scan input signal and output signal, each scan output signal directly coupled to the scan input signal of a succeeding flip-flop;
• and
• multiple functional data input signals coupled to a gate logic;
• and
• a circuit logic fixed between a pair of flip-flops.

A flip-flop, comprising:

• a plurality of flip-flop input signals;
• a transmission gate indirectly coupled to the plurality of flip-flop input signals;
• and
• a gate logic between the plurality of input signals and the transmission gate, wherein the gate logic is directly coupled to at least some of the plurality of input signals, and wherein the gate logic is not an inverter.

A flip-flop, comprising:

• a shifting logic comprising a plurality of clock input signals;
• wherein a first of the plurality of clock input signals causes a signal to be copied from a first data input signal to a first data output signal;
• and
• wherein a second of the plurality of clock input signals causes a signal to be copied from the first data output signal to a second data output signal.