High speed on chip testing

An integrated circuit having a selectively enabled clock doubler, comprising:

• an XOR gate for receiving a first signal on a first input and a second signal on a second input, and further for providing a third signal on an output,
• the first signal is a clock signal having a first frequency, where the clock signal is received from a tester on an input of the integrated circuit,
• a delay circuit for receiving the clock signal and delaying the clock signal by about ninety degrees,
• a control circuit for selectively activating the delay circuit to provide the delayed clock signal as the second signal, and selectively deactivating the delay circuit to provide a low signal as the second signal, where the control signal is selectively activated and deactivated by a signal received by the integrated circuit from the tester, and
• a buffer for receiving the third signal and providing the third signal as a buffered third signal,
• where the third signal has a third frequency, where the third frequency is about twice the first frequency when the second signal is the delayed clock signal and the third frequency is about the first frequency when the second signal is the low signal, and the third frequency is a higher frequency than the tester can produce.

A method for testing a high speed circuit on an integrated circuit at a high frequency that is higher than a tester frequency that is produced by a tester that is performing the testing, the method comprising the steps of:

• producing a tester clock signal having the tester frequency with the tester,
• providing the tester clock signal to the integrated circuit through a first input on the integrated circuit,
• routing the tester clock signal to a first input on an XOR gate,
• routing the tester clock signal to a delay circuit that is operable to produce a delayed clock signal at the tester frequency,
• producing a control signal with the tester,
• providing the control signal to the integrated circuit through a second input on the integrated circuit,
• routing the control signal to the delay circuit, where the control signal selectively engages and disengages the delay circuit based on tester settings,
• where the delay circuit produces the delayed clock signal as a delay circuit output when the delay circuit is engaged and the delay circuit produces a low signal as the delay circuit output when the delay circuit is disengaged,
• routing the delay circuit output to a second input on the XOR gate, thereby producing a test signal with the high frequency at an output of the XOR gate when the delay circuit is engaged and producing the test signal with the tester frequency when the delay circuit is disengaged, and
• selectively routing the test signal to the high speed circuit.