US 2006/0085703 A1 · Memory cell test circuit for use in semiconductor memory device and its method

Abstract

A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.

Claims27

Dependent claims

A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, comprising:

a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals;
a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line;
and
a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.

1 more element

A method for testing a memory cell included in a semiconductor memory device having a plurality of banks, comprising the steps of:

a) generating a first control clock signal and a second control clock signal based on a test mode signal and an input clock signal;
b) outputting data from the plurality of banks as a same logic level to a plurality of local input/output lines of the plurality of banks in response to the test mode signal;
c) outputting data outputted from the plurality of local input/output lines to a first to a fourth global input/output lines in response to a first control clock signal and a second control clock signal;
and
d) performing a logic operation to data of the first to the fourth global input/output lines and outputting a result of the logic operation to a test global input/output line.

2 more elements

Dependencies are inferred from the claim text.

Memory cell test circuit for use in semiconductor memory device and its method

Life of this patent

Memory cell test circuit for use in semiconductor memory device and its method

Life of this patent

Abstract

Claims27