Loading patent…
AssigneeCeva D.S.P. Ltd.
InventorsGil Drori, Erez Bar-Niv, David Dahan, Omri Eisenbach
Estimating the term…
A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.
A system for allowing a DMA (Direct Memory Access) controller to halt operation of at least one of a core processor and one or more breakpoint generating modules in a system providing mutual breakpoint capabilities, the system comprising:
A system for allowing a timer to halt operation of at least one of a core processor and one or more breakpoint generating modules in a system providing mutual breakpoint capabilities, the system comprising:
A method for halting operation of at least one breakpoint generating module and a core processor in a system providing mutual breakpoint capabilities in a computing device, the method comprising:
Dependencies are inferred from the claim text.