Cache memory system
OwnerTakanori Miyashita, Kohsaku Shibata +1inventors
InventorsTakanori Miyashita, Kohsaku Shibata, Shintaro Tsubata
Life of this patent
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Abstract
Provided is a cache memory system which, in a system having a plurality of masters, effectively utilizes a bus band. The cache memory system comprises: a cache memory; a bus load judging device for performing judgment of a state of a bus that is connected to a recording device in which cache-target data of the cache memory is stored; and a replace-way controller for controlling a replacing form of the cache memory according to a result of judgment performed by the bus load judging device.
Claims30
A cache memory system, comprising:
- a cache memory;
- a bus load judging device for performing judgment of a state of a bus that is connected to a recording device in which cache-target data of said cache memory is stored;
- and
- a replace-way controller for controlling a replacing form of said cache memory according to a result of said judgment performed by said bus load judging device.
A moving picture processor which processes inputted data and output it as moving picture data, said processor comprising:
- a cache memory;
- a bus load judging device for performing judgment of a state of a bus that is connected to a recording device in which cache-target data of said cache memory is stored;
- a replace-way controller for controlling a replacing form of said cache memory according to a result of said judgment performed by said bus load judging device;
- a controller for making an access to said cache memory;
- a recording device for recording a command of said controller or said data;
- a bus for transferring said command or said data between said controller and said recording device;
- and
- a bus controller for outputting information regarding said bus load to said bus load judging device.
A cache memory control method, comprising:
- a bus load judging step for judging a state of a bus that is connected to a recording device in which cache-target data of cache memory is stored;
- and
- a replace-way control step for controlling a replacing form of said cache memory according to a result of judgment performed in said bus load judging step.
Dependencies are inferred from the claim text.