Method for distinct count estimation over joins of continuous update stream
AssigneeAlcatel-Lucent USA Inc.
InventorsSumit Ganguly, Minos Garofalakis, Amit Kumar, Rajeev Rastogi
Life of this patent
Estimating the term…
Abstract
The invention provides methods and systems for summarizing multiple continuous update streams using corresponding multiple (parallel) JD Sketch data structures such that, for example, an approximate answer to a query requiring a join operation followed by a duplicate elimination step may be rapidly provided.
Claims26
A NOR flash memory device comprising:
- a cell array including banks each composed of sectors, each sector being constructed of memory cells coupled to wordlines and bitlines;
- a row selector to designate one of the wordlines in each bank in response to a row address;
- a column selector to designate bitlines in a unit of a predetermined number in each bank in response to a column address;
- a data input buffer to receive and hold program data bits in the unit of the predetermined number or less;
- and
- a program driver to contemporaneously apply a program voltage to the designated bitlines in response to the program data bits held in the data input buffer.
A system comprising:
- a host to generate data bits in units of a first predetermined number in a second predetermined number of times or less;
- and
- a NOR flash memory device operable in a program mode with the data bits supplied from the host, comprising:
- a cell array including banks disposed in correspondence with the second predetermined number of times, each bank being composed of sectors, each sector being constructed of memory cells coupled to wordlines and bitlines;
- a row selector to designate one of the wordlines in each bank in response to a row address;
- a column selector to designate bitlines in units of the first predetermined number in each bank in response to a column address;
- a data input buffer to receive and hold the data bits in the units of the first predetermined number in the second predetermined number of times or less;
- and
- a program driver to contemporaneously apply a program voltage to the designated bitlines in response to the data bits held in the data input buffer.
A method of programming a NOR flash memory device including a cell array with a number n banks each composed of sectors each of which is constructed of memory cells coupled to wordlines and bitlines, a row selector for designating one of the wordlines in each bank in response to a row address, and a column selector for designating units of i bitlines in each bank in response to a column address, the method comprising:
- receiving a command to enable a program operation of i data bits at the same time;
- receiving addresses to designate locations to store the data bits;
- receiving and temporarily holding the i data bits an n number of times or less, corresponding to the designated bitlines;
- and
- simultaneously applying a program voltage to the designated bitlines in response to the data bits temporarily held.
A NOR flash memory device comprising:
- a cell array including banks each composed of sectors, each sector being constructed of memory cells coupled to wordlines and bitlines;
- a row selector to designate one of the wordlines in each bank in response to a row address, the row selector including one row decoder for each one of the sectors;
- a column selector to designate bitlines in a unit of a predetermined number in each bank in response to a column address, the column selector including one column decoder for each one of the sectors;
- a data input buffer to receive and hold program data bits in the unit of the predetermined number or less;
- and
- a program driver to contemporaneously apply a program voltage to the designated bitlines in response to the program data bits held in the data input buffer.
Dependencies are inferred from the claim text.