CPU system, bus bridge, control method therefor, and computer system
AssigneeCanon Kabushiki Kaisha
InventorMasahiro Takizawa
Life of this patent
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Abstract
In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU 102 connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition request from the CPU (101), it controls acquisition of a semaphore on the basis of a semi_out signal received from the bus bridge (104) and a priority order received via a signal line (112).
Claims9
A CPU system having a plurality of CPUs and a plurality of bus bridges which are connected to the plurality of CPUs in one-to-one correspondence, wherein
- each of the plurality of bus bridges comprising:
- first reception means for receiving a semaphore acquisition request from a CPU connected to the bus bridge;
- second reception means for receiving, from remaining bus bridges, signals representing whether the remaining bus bridges have received semaphore acquisition requests from CPUs connected to the remaining bus bridges;
- and
- control means for, when the bus bridge receives a semaphore acquisition request by said first reception means, controlling acquisition of a semaphore on the basis of a signal received by said second reception means and a priority order set for the bus bridge.
A bus bridge which is connected to a CPU, comprising:
- first reception means for receiving a semaphore acquisition request from a CPU connected to the bus bridge;
- second reception means for receiving, from remaining bus bridges, signals representing whether the remaining bus bridges have received semaphore acquisition requests from CPUs connected to the remaining bus bridges;
- and
- control means for, when the bus bridge receives a semaphore acquisition request by said first reception means, controlling acquisition of a semaphore in accordance with a signal received by said second reception means and a priority order set for the bus bridge.
A method of controlling a CPU system having a plurality of CPUs and a plurality of bus bridges which are connected to the plurality of CPUs in one-to-one correspondence, wherein
- a method of controlling each of the plurality of bus bridges, comprising:
- a first reception step of receiving a semaphore acquisition request from a CPU connected to the bus bridge;
- a second reception step of receiving, from remaining bus bridges, signals representing whether the remaining bus bridges have received semaphore acquisition requests from CPUs connected to the remaining bus bridges;
- and
- a control step of, when the bus bridge receives a semaphore acquisition request in the first reception step, controlling acquisition of a semaphore on the basis of a signal received in the second reception step and a priority order set for the bus bridge.
A method of controlling a bus bridge connected to a CPU, comprising:
- a first reception step of receiving a semaphore acquisition request from a CPU connected to the bus bridge;
- a second reception step of receiving, from remaining bus bridges, signals representing whether the remaining bus bridges have received semaphore acquisition requests from CPUs connected to the remaining bus bridges;
- and
- a control step of, when the bus bridge receives a semaphore acquisition request in the first reception step, controlling acquisition of a semaphore in accordance with a signal received in the second reception step and a priority order set for the bus bridge.
Dependencies are inferred from the claim text.