Snoop filter directory mechanism in coherency shared memory system
AssigneeInternational Business Machines Corporation
InventorsRussell Hoover, Eric Mejdrich, Jon Kriegel, Sandra Woodward
Life of this patent
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Abstract
Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
Claims24
A method of maintaining coherency of data accessed by a remote device, comprising:
- maintaining, on the remote device, a remote cache directory indicative of memory locations residing in a cache on a processor which shares access to some portion of a memory device;
- maintaining, on the remote device, a castout buffer indicating cache lines that have been or will be castout from the processor cache;
- and
- routing memory requests issued at the remote device to the memory device or the processor cache, depending on information contained in the remote cache directory and castout buffer.
A method of maintaining coherency of data accessed by a remote device, comprising:
- maintaining, on the remote device, a remote cache directory indicative of memory locations residing in a cache on a processor which shares access to some portion of a memory device;
- routing a memory request issued at the remote device to the processor cache if an address targeted by the memory request matches an entry in the remote cache directory;
- and
- creating an entry in an outstanding transaction buffer residing on the remote device, the entry containing the address targeted by the memory request routed to the processor cache.
A device configured to access data stored in memory and cacheable by a processor, comprising:
- one or more processing cores;
- a remote cache directory indicative of contents of a cache residing on the processor;
- a castout buffer indicating cache lines that have been or will be castout from the processor cache;
- and
- coherency logic configured to receive cache coherency information indicative of changes to the contents of the processor cache sent by the processor in bus transactions and update the cache directory and castout buffer based on the cache coherency information.
A coherent system, comprising:
- a processor having a cache for storing data accessed from external memory, a cache directory with entries indicating which memory locations are stored in cache lines of the cache and corresponding coherency states thereof, and control logic configured to detect internal bus transactions indicating the allocation and de-allocation of cache lines and, in response, generate bus transactions, each containing cache coherency information indicating cache line that has been allocated or de-allocated;
- and
- a remote device having a remote cache directory indicative of contents of the cache residing on the processor, a castout buffer indicating cache lines that have been or will be castout from the processor cache, and coherency logic configured to update the remote cache directory, based on cache coherency information contained in the external bus transactions generated by the processor control logic, to reflect allocated and de-allocated cache lines of the processor cache.
Dependencies are inferred from the claim text.