Bus bridge and data transfer method
AssigneeFujitsu Limited
InventorYoshihiro Hiji
Life of this patent
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Abstract
In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.
Claims10
A bus bridge that is connected between a high-speed bus line and a low-speed bus line, wherein a high-speed device is connected to the high-speed bus line and a low-speed device is connected to the low-speed bus line, comprising:
- a buffer unit that temporarily stores data that is read from the low-speed device via the low-speed bus line;
- a register that stores a value of a valid flag that indicates that valid data is stored in the buffer unit;
- and
- a control logic unit that performs a control to successively transfer the data from the low-speed device to the high-speed device predetermined number times, wherein
- the control includes releasing the high-speed bus line before completion of reading of the data from the low-speed device, storing the data read from the low-speed device in the buffer unit, setting a value in the register to indicate that valid data is stored in the buffer unit, confirming, at a following access in a series of accesses to the high-speed device, that a value stored in the register indicates that valid data is stored in the buffer unit, and outputting the data from the buffer unit to the high-speed device.
A data transfer method for successively transferring data from a low-speed device to a high-speed device via a bus bridge that is connected between a high-speed bus line and a low-speed bus line predetermined number times, the low-speed device being connected to the low-speed bus line, the high-speed device being connected to the high-speed bus line, comprising:
- releasing the high-speed bus line before completion of reading of data from the low-speed device;
- temporarily storing the data read from the low-speed device in the bus bridge;
- and
- outputting the data from the bus bridge to the high-speed device at a following access in a series of accesses to the high-speed device.
Dependencies are inferred from the claim text.