Multi-threaded DMA
AssigneeTexas Instruments Incorporated
InventorsFranck Seigneret, Sivayya Ayinala, Nabil Khalifa, Praveen Kolli, Prabha Atluri
Life of this patent
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Abstract
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
Claims20
A direct memory access (DMA) circuit, comprising:
- a read port;
- a read port scheduler coupled to the read port;
- a write port;
- a write port scheduler coupled to the write port;
- a request port coupled to the read and write port schedulers;
- and
- the read port can support “m” threads and the write port can support “n” threads, where each thread can support either a single access or a burst access transaction and the read and write ports can work on different data transfers at the same time.
A multithreading direct memory access (DMA) circuit comprising:
- a write port;
- a read port;
- a memory coupled to both the read and write ports;
- and
- a means coupled to the memory for mapping requests and logical channels.
Dependencies are inferred from the claim text.