Method and apparatus for simultaneous bidirectional signaling in a bus topology
AssigneeRambus Inc.
InventorFrederick Ware
Life of this patent
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Abstract
A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction.
Claims39
A method for providing simultaneous bidirectional signaling in a bus topology comprising the steps of:
- selecting a first device and a second device from among a plurality of devices operably coupled to a common bus to exchange a first set of data;
- scheduling a first exchange slot over which the first device and the second device are to exchange the first set of data;
- and
- during the first exchange slot, simultaneously transmitting a first portion of the first set of data from the first device to the second device over the common bus and transmitting a second portion of the first set of the data from the second device to the first device over the common bus.
A system providing simultaneous bidirectional signaling using a bus topology, the system comprising:
- a first device operably coupled to a bus;
- a second device operably coupled to the bus, the first device transmitting a first portion of a first set of data to the second device and the second device transmitting a second portion of the first set of data to the first device simultaneously during a first exchange slot;
- and
- a third device operably coupled to the bus, the first device transmitting a first portion of a second set of data to the third device and the third device transmitting a second portion of the second set of data to the first device simultaneously during a second exchange slot.
A device coupled to a bus in a bus topology capable of simultaneous bidirectional signaling, the device comprising:
- a driver capable of additive signaling, said driver circuit applying transmit signals to the bus;
- a receiver circuit operably coupled to the driver, the receiver circuit capable of effectively subtracting the transmit signals to receive received signals from the bus, the driver and the receiver circuit operating during an exchange slot.
A memory system comprising:
- a memory controller;
- a bus operably coupled to the memory controller;
- a first memory device operably coupled to the bus, the first memory device adapted to simultaneously send first read data to the memory controller via the bus and receive first write data from the memory controller via the bus;
- and
- a second memory device operably coupled to the memory controller, the second memory device adapted to simultaneously send second read data to the memory controller via the bus and receive second write data from the memory controller via the bus.
A memory device adaptable to be coupled to a bus comprising:
- a driver adapted to drive the bus with read data during an exchange slot while write data are present on the bus;
- a receiver circuit operably coupled to the driver, the receiver circuit capable of receiving the write data from the bus during the exchange slot while the driver is driving the bus with the read data;
- and
- a memory circuit operably coupled to the receiver circuit, the memory circuit adapted to provide the read data and to store the write data.
A memory controller adapted to be coupled to a bus comprising:
- a driver adapted to drive the bus with first write data destined for a first memory device during a first exchange slot while first read data from the first memory device are present on the bus;
- a receiver circuit operably coupled to the driver, the receiver circuit adapted to receive the first read data from the bus during the first exchange slot while the driver is driving the bus with the first write data.
A method for providing simultaneous bidirectional communication between a memory controller and a plurality of memory devices comprising the steps of:
- during a first exchange slot, simultaneously communicating over a common bus first write data from the memory controller to a first memory device of the plurality of memory devices and first read data from the first memory device to the memory controller;
- and
- during a second exchange slot, simultaneously communicating over a common bus second write data from the memory controller to a second memory device of the plurality of memory devices and second read data from the second memory device to the memory controller.
A system for bidirectional communication of data over a common bus comprising:
- a first device operably coupled to the common bus, the first device comprising a first-to-second transmit buffer to hold first-to-second data and a first-to-third transmit buffer to hold first-to-third data;
- a second device operably coupled to the common bus, the second device comprising a second-to-first transmit buffer to hold second-to-first data;
- a third device operably coupled to the common bus, the third device comprising a third-to-first transmit buffer to hold third-to-first data;
- a scheduler operably coupled to the common bus, the scheduler scheduling the first device to transmit the first-to-second data and the second device to transmit the second-to-first data over the common bus during a first exchange slot and scheduling the first device to transmit the first-to-third data and the third device to transmit the third-to-first data over the common bus during a second exchange slot, the scheduler introducing a turnaround delay sufficient to prevent inter-symbol interference between the first exchange slot and the second exchange slot.
Dependencies are inferred from the claim text.