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US 2006/0079043 A1Published application
Method of manufacturing semiconductor integrated circuit device
AssigneeSeiko Instruments Inc.
InventorJun Osanai
Life of this patent
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Abstract
A method of manufacturing a MOS transistor having sufficiently many Vth's is provided by selectively arranging a nitride film to overlap with the source and the gate electrode of the MOS transistor, and by varying an overlap amount of the nitride film with respect to the gate electrode in a channel width direction in accordance with the design value for the pattern.
Claims4
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
- forming a gate electrode;
- forming an insulating film on the gate electrode and on regions to be a source and a drain respectively;
- forming the source and the drain;
- and
- selectively forming a nitride film extending over the source and the gate electrode, on the insulating film.
2 more elements
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
- forming a gate electrode;
- forming an insulating film on the gate electrode and on regions to be a source and a drain respectively;
- forming the source and the drain;
- and
- selectively forming a nitride film extending over the drain and the gate electrode, on the insulating film.
2 more elements
Dependencies are inferred from the claim text.