Method for manufacturing wafer level chip scale package using redistribution substrate
AssigneeEasetech Korea Co., Ltd.
InventorJae-June Kim
Life of this patent
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Abstract
The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.
Claims24
A method for manufacturing a wafer level chip scale package, the method comprising:
- (a) producing a redistribution substrate having a transparent insulating substrate and redistribution lines formed on the transparent insulating substrate;
- (b) providing a wafer having a semiconductor substrate having an active surface and at least one non-active surface, the wafer further having chip pads formed on the active surface;
- (c) bonding the redistribution substrate to the wafer so that first parts of the redistribution lines are connected with the chip pads;
- (d) forming holes extended from the active surface to the non-active surface in the wafer so that the second parts of the redistribution lines are exposed to the holes;
- (e) forming conductive lines in the holes and on the non-active surface;
- (f) forming external connection terminals on the conductive lines formed on the non-active surface;
- and
- (g) dividing both the redistribution substrate and the wafer along a scribe line.
Dependencies are inferred from the claim text.