Synchronization signal detection circuit and method of digital television (DTV) receiver

A digital TV (DTV) reception apparatus comprising:

• a demodulator which converts an analog Vestigial Sideband (VSB) signal extracted by a tuner into a digital signal and generates a real component signal and an imaginary component signal of the digital signal;
• a synchronization signal detection circuit which determines a main path signal and a field direction signal based on correlation values obtained using the real component signal and the imaginary component signal and generates a phase offset value for the VSB signal, a segment synchronization signal, and a plurality of synchronization signals based on the determined main path signal and the determined field direction signal, the synchronization signals being synchronized with the segment synchronization signal;
• wherein the synchronization signal detection circuit comprises:
• a first power calculator that calculates a first power signal based on the real component signal and the imaginary component signal;
• a main path detector that generates a main path position signal based on the calculated power signal.

A DTV reception method comprising:

• converting an analog VSB signal extracted by a tuner into a digital signal;
• generating a real component signal and an imaginary component signal by demodulating the digital signal;
• determining a main path signal and a field direction signal based on correlation values obtained using the real component signal and the imaginary component signal;
• generating a phase offset value for the VSB signal, a segment synchronization signal, and a plurality of synchronization signals based on the determined main path signal and the determined field direction signal, the synchronization signals being synchronized with the segment synchronization signal;
• compensating for the phase of the real component signal using the phase offset value and outputting the compensated result;
• filtering the compensated result through distortion compensation and outputting the filtered result;
• performing an error correction operation on the filtered result and outputting an error obtained during the error correction operation;
• and
• determining whether to lock the synchronization signals according to a locking cancellation control signal.