Carrier phase and symbol timing recovery circuit for an ATSC receiver and method of recovering a carrier phase and a symbol timing in received digital signal data
AssigneeSamsung Electronics Co., Ltd.
InventorsSergey Zhidkov, Min-ho Kim
Life of this patent
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Abstract
A carrier phase and symbol timing recovery circuit and method may be used for robust synchronization in a broadcasting ATSC receiving system. Carrier phase and symbol timing offsets may be simultaneously adjusted by using redundancy information contained in an ATSC signal spectrum. A desired sampling time instant and carrier phase offset for synchronization may be simultaneously obtained due to correlation between carrier phase and symbol timing detectors.
Claims36
A carrier phase and symbol timing recovery circuit for recovering a carrier phase and a symbol timing in received digital signal data, comprising:
- a pilot-based error detector detecting a first phase error based on a pilot signal included in the received digital signal data;
- a lower error detector detecting a second phase error based on data in a lower overlapped region where a lower portion of an information-containing signal included in the received digital signal data overlaps a replica of the information-containing signal;
- an upper detector detecting a third phase error based on data in an upper overlapped region where an upper portion of the information-containing signal overlaps a replica of the information-containing signal;
- a first calculation unit determining a carrier phase offset value from the detected first, second and third phase errors;
- and
- a second calculation unit determining a symbol timing offset value from the detected first, second and third phase errors,
- wherein a desired sampling time instant and carrier phase offset are detected at a point where the determined carrier phase offset and symbol timing offset values are each zero, so as to simultaneously recover a carrier phase and a symbol timing in the received digital signal data.
A method of recovering a carrier phase and a symbol timing in received digital signal data, comprising:
- detecting first, second and third phase errors based on one or more of a pilot signal and an information-containing signal included in the received digital signal data,
- determining a carrier phase offset value as a function of the detected first, second and third phase errors, and
- determining a symbol timing offset value as a function of the detected first, second and third phase errors,
- wherein a desired sampling time instant and carrier phase offset are detected at a point where the determined carrier phase offset and symbol timing offset values are each zero, so as to simultaneously recover a carrier phase and a symbol timing in the received digital signal data.
A circuit for recovering a carrier phase and a symbol timing in received digital signal data, comprising:
- a first error detector detecting a first phase error,
- a second error detector detecting a second phase error,
- a third error detector detecting a third phase error,
- a first addition/subtraction unit determining a carrier phase offset value as a function of the detected first, second and third phase errors, and
- a second addition/subtraction unit determining a symbol timing offset value as a function of the detected first, second and third phase errors,
- wherein a desired sampling time instant and carrier phase offset are detected at a point where the determined carrier phase offset and symbol timing offset values are each zero, so as to simultaneously recover a carrier phase and a symbol timing in the received digital signal data.
A circuit for recovering a carrier phase and a symbol timing in received digital signal data, comprising:
- an error detector generating a first phase error,
- means for generating a second phase error,
- means for generating a third phase error, the third phase error equal to the second phase error,
- a first addition/subtraction unit determining a carrier phase offset value as a function of the first, second and third phase errors, and
- a second addition/subtraction unit determining a symbol timing offset value as a function of the detected first, second and third phase errors,
- wherein a desired sampling time instant and carrier phase offset are detected at a point where the determined carrier phase offset and symbol timing offset values are each zero, so as to simultaneously recover a carrier phase and a symbol timing in the received digital signal data.
Dependencies are inferred from the claim text.