On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture

A semiconductor device comprising an on-chip bus, the on-chip bus including:

• a plurality of switch points including first and second switch points;
• a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point;
• and
• a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point;
• wherein data transmitted from the first functional block core to the second functional block core passes through the first switch point without traversing any of the plurality of inter-switch links.

A method for communicating data on an on-chip bus, the method comprising:

• receiving data from a source functional block core at a first switch point coupled to the source functional block core;
• determining whether or not a destination functional block core is directly coupled to the first switch point;
• sending the data to the destination functional block core through the first switch point when the destination functional block core is directly coupled to the first switch point;
• and
• sending the data to the destination functional block core through at least one inter-switch link and at least one second switch point arranged between the first switch point and the destination functional block core when the destination functional block core is not directly coupled to the switch point.