System and method for error detection in a redundant memory system
AssigneeDell Products L.P.
InventorJohn Pescatore
Life of this patent
Estimating the term…
Abstract
A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical mirroring scheme. A cyclic redundancy code is generated on the basis of the data bits and address bits. The generated cyclic redundancy code and a copy of the cyclic redundancy code are saved to the memory channels according to a horizontal mirroring scheme or a vertical mirroring scheme.
Claims20
A method for identifying errors in the memory of a computer system, comprising:
- generating a set of cyclic redundancy code bits from a set of data bits and associated address bits;
- saving the data bits and the cyclic redundancy code bits to a first memory location;
- saving a duplicate of the data bits and the cyclic redundancy code bits to a second memory location;
- retrieving the data bits and the cyclic redundancy code bits from the first memory location;
- generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits and associated address bits;
- and
- comparing the retrieved cyclic redundancy code bits with the second set of the cyclic redundancy code bits.
A method for identifying errors in the memory of a computer system, comprising:
- generating a set of cyclic redundancy code bits from a set of data bits and respective address bits;
- saving a first portion of the data bits and the cyclic redundancy bits to a first memory location;
- saving a duplicate of the first portion of the data bits and the cyclic redundancy bits to a second memory location;
- saving a second portion of the data bits and the cyclic redundancy bits to a second memory location;
- saving a duplicate of the second portion of the data bits and the cyclic redundancy bits to a first memory location
- retrieving the first portion of the data bits and the cyclic redundancy code bits from the first memory location and the second portion of the data bits and the cyclic redundancy code bits from the second memory location;
- generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits;
- and
- comparing the retrieved cyclic redundancy code bits with the second set of the cyclic redundancy code bits.
A memory subsystem, comprising:
- a memory controller;
- a first memory channel coupled to the memory controller, the first memory channel comprising a plurality of memory lines for storing a code word comprising a set of data bits and a cyclic redundancy code generated on the basis of the set of data bits and corresponding address bits;
- and
- a second memory channel couple to the memory controller, the second memory channel comprising a plurality of memory lines for storing a duplicate of the data bits and cyclic redundancy code of the first memory channel.
A memory subsystem, comprising:
- a memory controller;
- a first memory channel coupled to the memory controller, the first memory channel comprising a plurality of memory lines for storing a first portion of a code word, a first portion of a cyclic redundancy code generated on the basis of the code word, a duplicate of the second portion of the code word, and a duplicate of the second portion of a cyclic redundancy code generated on the basis of the code word;
- and
- a second memory channel coupled to the memory controller, the second memory channel comprising a plurality of memory lines for storing a duplicate of the first portion of a code word, a duplicate of the first portion of a cyclic redundancy code generated on the basis of the code word, a second portion of the code word, and a second portion of a cyclic redundancy code generated on the basis of the code word.
Dependencies are inferred from the claim text.