System and method for avoiding offset in and reducing the footprint of a non-volatile memory
AssigneeAtmel Corporation
InventorsMassimiliano Frulio, Riccardo Reggiori, Andrea Sacco, Luca Figini
Life of this patent
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Abstract
A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
Claims14
A non-volatile memory comprising:
- a plurality of banks of memory cells;
- a plurality of sets of sense amplifiers coupled to the plurality of banks of memory cells and each of sense amplifiers configured to perform memory operations;
- a plurality of biasing circuits coupled to the plurality of banks of memory cells;
- and
- a reference cell matrix coupled to the plurality of biasing circuits and configured to provide reference cell current to the plurality of biasing circuits and to the plurality of sense amplifiers.
A system for avoiding offset and reducing the footprint of a non-volatile memory, the system comprising:
- a plurality of memory bank circuits, each memory bank circuit having a plurality of memory cells;
- a plurality of sense amplifiers coupled to the plurality of memory cells;
- a plurality of row and column decoders coupled to the memory cells;
- a plurality of bias circuits coupled to the plurality of sense amplifiers;
- and
- a reference cell matrix coupled to each of the plurality of memory bank circuits and configured to provide reference cell current for each of the plurality of memory bank circuits.
A method for avoiding offset and reducing the footprint of a non-volatile memory having a plurality of memory bank circuits, each memory bank circuit having memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers, the system comprising:
- connecting a reference cell matrix to each of the plurality of memory bank circuits;
- and
- providing reference cell current for each of the plurality of memory bank circuits.
Dependencies are inferred from the claim text.