Integrated circuit device provided with series-connected TC parallel unit ferroelectric memory and method for testing the same

An integrated circuit device comprising:

• a memory cell block comprising memory cells connected in series, the memory cell comprising a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor including electrodes connected to terminals of the cell transistor;
• a first address buffer circuit which latches an address signal and outputs the address signal, an address signal identifying one of the word lines connected to the cell transistors in the memory cell block,
• a second address buffer circuit which outputs the address signal without latching the address signal;
• a switching circuit which receives the address signals output from the first address buffer circuit and the second address buffer circuit, and then outputs the address signal output from the first address buffer circuit in a regular operation time in which one of writing and reading is performed, and outputs the address signal output from the second address buffer circuit in a test mode in which a test is carried out on the memory cells;
• a word line selecting circuit which selects the one of the word lines connected to the cell transistors, in response to the address signal output from the switching circuit;
• and
• a driving circuit which applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period in which the one of the word lines is selected in response to the address signal output from the second address buffer circuit.

A method for testing an integrated circuit device which comprises a memory cell block comprising memory cells connected in series, the memory cell comprising a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor including electrodes connected to terminals of the cell transistor, the method comprising:

• turning off a first cell transistor of the cell transistors, which is included in a first memory cell of the memory cells in the memory cell block, and tuning on the other transistors of the cell transistors, which are included in the other memory cells;
• turning off a second cell transistor adjacent to the first cell transistor;
• turning on the first cell transistor after turning off the second cell transistor;
• and
• applying a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, from time the first cell transistor is turned off to time the first cell transistor is turned on.