System for format conversion using clock adjuster and method of the same
AssigneeMediatek Inc.
InventorJen-Shi Wu
Life of this patent
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Abstract
A system and same method are provided for producing video signal timing to a display apparatus that has different input/output image/video format. In addition to an image scaler, the system comprises a clock adjuster including a first and a second clock generator. The first clock generator generates a first clock signal by which the input/source pixel data included in the input/source image frame are received. The second clock signal is generated and adjusted to have an average clock period such that the ratio of the input and output frame rates is substantially kept constant. Thus, the skew between the source/input images and the display/output images can be adjusted, and the output frame repeating and/or dropping can be avoided.
Claims20
A method of converting a source image frame in vertical and/or horizontal directions to generate a destination image frame, the source image frame being received at an input frame rate and including a plurality of source scan lines having a plurality of source pixel data, the destination image frame being outputted at an output frame rate and including a plurality of destination scan lines having a plurality of destination pixel data, said method comprising the following steps of:
- (a) receiving the plural source pixel data included in the source image frame by using a first clock signal or a data valid signal (CLK_src);
- (b) generating an estimated source horizontal signal (HSYNC_src′) by using a second clock signal (CLK_dst);
- (c) scaling the source image frame in vertical and/or horizontal directions to generate the plural destination pixel data representative of the destination image frame;
- and
- (d) providing the plural destination pixel data representative of the destination image frame by using an adjusted second clock signal;
- wherein the adjusted second clock signal is generated to have an average clock period such that the ratio of the input and output frame rates is substantially kept constant.
A system for converting a source image frame in vertical and/or horizontal directions to generate a destination image frame, the source image frame being received at an input frame rate and including a plurality of source scan lines having a plurality of source pixel data, the destination image frame being outputted at an output frame rate and including a plurality of destination scan lines having a plurality of destination pixel data, said system comprising:
- a first timing generator, for receiving the plural source pixel data included in the source image frame by using a first clock signal or a data valid signal (CLK_src) to generate a source horizontal synchronization signal (HSYNC_src);
- a second timing generator, for generating an estimated horizontal signal (HYSNC_src′) by using a second clock signal (CLK_dst);
- an image scaler for scaling the source image frame in vertical and/or horizontal directions to generate the plural destination pixel data representative of the destination image frame using an adjusted second clock signal;
- wherein the adjusted second clock signal is generated to have an average clock period such that the ratio of the input and output frame rates is substantially kept constant.
Dependencies are inferred from the claim text.