Analog front end timing generator (AFE/TG) having a bit slice output mode

A method of outputting pixel information from an integrated circuit, the integrated circuit having a first plurality of terminals and a second plurality of terminals, the method comprising:

• in a first mode outputting at least part of a first multi-bit pixel value by outputting a first subset of bits of the first multi-bit pixel value onto the first plurality of terminals at a first time and then outputting a second subset of the bits of the first multi-bit value onto the first plurality of terminals at a second time;
• and
• in a second mode outputting a second multi-bit pixel value by outputting a first plurality of bits of the second multi-bit pixel value onto the first plurality of terminals at the same time that a second plurality of the bits of the second multi-bit pixel value is output onto the second plurality of terminals, the integrated circuit being operable in a selectable one of the first mode and the second mode.

A method of outputting pixel information from a timing generator integrated circuit, the timing generator integrated circuit having a first plurality of terminals and a second plurality of terminals, the method comprising:

• in a first mode outputting at least part of a first multi-bit pixel value by outputting a first subset of bits of the first multi-bit pixel value onto the first plurality of terminals at a first time and then outputting a second subset of the bits of the first multi-bit value onto the first plurality of terminals at a second time and then outputting a third subset of the bits of the first multi-bit value onto the first plurality of terminals at a third time.

A method of outputting pixel information from a timing generator integrated circuit, the timing generator integrated circuit having a first plurality of terminals and a second plurality of terminals, the timing generator integrated circuit being operable in a selectable one of a first mode and a second mode, the method comprising:

• wherein if the timing generator integrated circuit is operating in the first mode then the timing generator integrated circuit outputs at least part of a multi-bit pixel value by outputting a first subset of bits of the multi-bit pixel value onto the first plurality of terminals at a first time and then outputting a second subset of the bits of the multi-bit value onto the first plurality of terminals at a second time and then outputting a third subset of the bits of the multi-bit value onto the first plurality of terminals at a third time;
• and
• wherein if the timing generator integrated circuit is operating in the second mode then the timing generator integrated circuit outputs the multi-bit pixel value by outputting a first plurality of bits of the multi-bit pixel value onto the first plurality of terminals at the same time that a second plurality of the bits of the multi-bit pixel value is output onto the second plurality of terminals, the multi-bit pixel value consisting of the first plurality of bits and the second plurality of bits.