Thin film transistor array plate, liquid crystal display panel and method of preventing electrostatic discharge

A liquid crystal display panel, comprising:

• a color filter plate;
• a thin film transistor array plate, having a display region and a peripheral circuit region, comprising:
• a plurality of pixel structures, disposed inside the display region;
• a plurality of switching devices, disposed inside the peripheral circuit region;
• a plurality of lead lines, disposed on the substrate, wherein each lead line electrically connects the corresponding pixel structures and one of the switching devices;
• and
• a plurality of electrostatic discharge (ESD) protection circuits, disposed inside the peripheral circuit region, wherein each one of the ESD protection circuits is electrically connected to portions of the switching devices;
• and
• a liquid crystal layer, disposed between the color filter plate and the thin film transistor array plate.

A thin film transistor array plate, comprising:

• a substrate, having a display region and a peripheral circuit region;
• a plurality of gate lines, disposed on the substrate;
• a plurality of source lines, disposed on the substrate, wherein the gate lines and the source lines define the display region into a plurality of pixel areas;
• a plurality of thin film transistor, each thin film transistor disposed inside one of the pixel area, wherein each one of the thin film transistors is electrically connected to one of the gate lines and one of the source lines correspondingly;
• a plurality of pixel electrode, each pixel electrode positioned inside one of the pixel areas and electrically connected to a corresponding thin film transistor;
• a plurality of switching devices, disposed inside the peripheral circuit region, wherein each one of the switching devices is electrically connected to one of the gate lines and the source lines;
• a first electrostatic discharge protection circuit, disposed inside the peripheral circuit region, wherein the first electrostatic discharge protection circuit is electrically connected to odd numbered gate lines through portions of the switching devices;
• a second electrostatic discharge protection circuit, disposed inside the peripheral circuit region, wherein the second electrostatic discharge protection circuit is electrically connected to even numbered gate lines through portions of the switching devices;
• a third electrostatic discharge protection circuit, disposed inside the peripheral circuit region, wherein the third electrostatic discharge protection circuit is electrically connected to odd numbered source lines through portions of the switching devices;
• and
• a fourth electrostatic discharge protection circuit, disposed inside the peripheral circuit region, wherein the fourth electrostatic discharge protection circuit is electrically connected to even numbered source lines through portions of the switching devices.