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US 2006/0077078 A1Published application
Command user interface with programmable decoder
AssigneeMicron Technology, Inc.
InventorsPasquale Pistilli, Elio D'Ambrosio
Life of this patent
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Abstract
A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.
Claims46
A method for re-encoding a decoder, the method comprising:
- changing only via locations in an insulating layer to effect re-encoding, wherein a via location defines a contact to which a gate of a transistor is coupled.
A memory device, comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections, and;
- a command user interface connected to the ROM to control commands for the ROM, the CUI comprising:
- a decoder having a plurality of series-connected transistors whose gates are selectively coupled to receive either an input or its complement using vias;
- and
- a plurality of latches to latch input and output data for the command user interface.
4 more elements
A memory device, comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections, and;
- a command user interface connected to the ROM to control commands for the ROM, the CUI comprising:
- a plurality of transistors connected in series, each transistor having first and second contacts hard programmed to a low logic value and a high logic value respectively;
- a plurality of vias each connectable between a gate of one of the plurality of transistors and the first or the second contact to hard program the low logic value or the high logic value;
- and
- a plurality of latches to latch input and output data for the command user interface.
5 more elements
A memory device, comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections, and;
- a command user interface connected to the ROM to control commands for the ROM, the CUI comprising:
- a plurality of decoders, each decoder having a series of transistors whose gates are selectively coupled to receive either an input or its complement using vias;
- and
- a plurality of latches to latch input and output data for the command user interface.
4 more elements
A memory device, comprising:
- an array of non-volatile memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections, and;
- a decoder connected to the array to control commands for the array, the decoder comprising:
- a first decoder section comprising:
- a plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a pair of contacts;
- and
- a pair of contacts for each transistor, each contact coupled to the input or to the complement of the input through a via.
5 more elements
A memory device, comprising:
- an array of non-volatile memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections, and;
- a programmable decoder connected to the array to control commands for the array, the programmable decoder comprising:
- a first decoder section coupled to decode data from the first input, the first decoder section comprising:
- a plurality of transistors connected in series;
- and
- a plurality of contacts, each contact coupled to either the input or the complement of the input, wherein the vias connect a gate of a single transistor of the plurality of transistors to either the input or to the complement of the input;
- and
- a second decoder section substantially identical to the first decoder section, and connected in series with the first decoder section, the second decoder section coupled to decode data from the second input.
7 more elements
Dependencies are inferred from the claim text.