Apparatus and methods for saving power and reducing noise in integrated circuits

A power saving circuit for operation between a positive voltage supply and negative voltage supply, said power saving circuit comprising:

• electronic circuitry that is implemented in CMOS technology, said electronic circuitry having a positive voltage terminal and a negative voltage terminal,
• a first impedance disposed between the positive voltage supply and the positive voltage terminal of the electronic circuitry,
• a second impedance disposed between the negative voltage supply and the negative voltage terminal of the electronic circuitry, and
• a capacitor disposed between the positive voltage terminal and the negative voltage terminal of the electronic circuitry, said electronic circuitry operating from a pseudo voltage supply across the capacitor.

An electronic noise reduction circuit for operation between a positive voltage supply and a negative voltage supply, said electronic noise reduction circuit comprising:

• electronic circuitry that is implemented in CMOS technology, said electronic circuitry having a positive voltage terminal and a negative voltage terminal,
• a first impedance disposed between the positive voltage supply and the positive voltage terminal of the electronic circuitry,
• a second impedance disposed between the negative voltage supply and the negative voltage terminal of the electronic circuitry, and
• a capacitor disposed between the positive voltage terminal and the negative voltage terminal of the electronic circuitry,
• said electronic circuitry operating from a pseudo voltage supply across the capacitor.

In an integrated circuit, a method for supplying power to internal circuits within the integrated circuit, comprising the steps of:

• providing first and second power supply nodes for first and second voltages respectively;
• coupling a first supply voltage to said first supply node;
• coupling a second supply voltage to said second supply node;
• providing a capacitor between said first and second supply nodes;
• coupling active circuits between said first and second supply nodes;
• using voltage stored in said capacitor for driving said active circuits;
• and
• capturing switching currents in said capacitor.

A method for supplying power to internal circuits in an integrated circuit, said method comprising the steps of:

• providing first and second nodes for supplying first and second pseudo power supply voltages respectively;
• selectively coupling a first supply voltage to said first supply node via a first supply control transistor;
• selectively coupling a second supply voltage to said second supply node via a second supply control transistor;
• connecting a capacitor between said first and second nodes;
• coupling active circuits between said first and second nodes;
• developing pseudo power supply voltages, at said capacitor and at said first and second nodes;
• and
• using said pseudo power supply voltages to power said active circuits.

A method for reducing power consumption in an integrated circuit, said method comprising the steps of:

• using crowbar currents to charge a capacitor;
• supplying voltage from said capacitor to active circuits in the integrated circuit;
• and
• selectively charging said capacitor from a power source other than said active circuits.

A method for supplying power to internal circuits within an integrated circuit, said method comprising the steps of:

• providing a power supply node for a first voltage;
• coupling a first voltage to said power supply node;
• providing a capacitor between said power supply node and ground or between said power supply node and a second voltage;
• coupling active circuits between said power supply node and ground or between said power supply node and the second voltage;
• using voltage stored in said capacitor for driving said active circuits;
• and
• capturing switching currents in said capacitor.