US 2006/0076993 A1 · High speed clock and data recovery system

Abstract

A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate the condition. The system can also include a time varying gain adjustment portion. This portion includes a gain control logic configured to determine and adjust system gain during reception of an incoming data stream. The system further includes a phase interpolator having increased linearity. The phase interpolator has a plurality of first branches having a differential transistor pair, a switch, and a current source, coupled between a first output and a first supply voltage and a plurality of second branches having a differential transistor pair, a switch, and a current source, coupled between a second output and the first supply voltage. The phase interpolator can also include an integrator portion.

Claims57

Dependent claims

A clock and data recovery system comprising:

a start of packet detector for detecting the start of a preamble of an incoming data stream;
a gain control logic module coupled to the start of packet detector, wherein the gain control logic module is configured to determine a gain value;
a phase interpolator for generating a recovered clock signal;
a sampling module coupled to the phase interpolator, the sampling module including logic for sampling a data stream using the recovered clock signal;
a phase detector coupled to the sampling module, wherein the phase detector generates a phase adjustment signal;
a gain adjust module coupled to the phase detector, the gain control logic module, and a phase accumulator, wherein the gain adjust module applies the gain value received from the gain control logic module to the phase adjustment signal;
and
a phase accumulator coupled to the gain adjust module and the phase interpolator.

5 more elements

A phase interpolator comprising:

a voltage integrator;
a plurality of first branches, wherein each of the first branches includes:
a first transistor receiving a first signal at its gate, wherein a drain of the first transistor is coupled to a first output,
a second transistor receiving a second signal at its gate, wherein a drain of the second transistor is coupled to a second output,
a first switch coupled to a source of the first transistor and a source of the second transistor, and
a first current source coupled to the switch and a first supply voltage;
a plurality of second branches, wherein each of the second branches includes:
a third transistor receiving a third signal at its gate, wherein a drain of the third transistor is coupled to the first output,
a fourth transistor receiving a fourth signal at its gate, wherein a drain of the fourth transistor is coupled to the second output,
a second switch coupled to a source of the third transistor and a source of the fourth transistor, and
a second current source coupled to the switch and a first supply voltage.

8 more elements

A system comprising:

a phase interpolator, wherein the phase interpolator includes:
a plurality of first branches, wherein each of the first branches has:
a first transistor receiving a first signal at its gate, wherein a drain of the first transistor is coupled to a first output,
a second transistor receiving a second signal at its gate, wherein a drain of the second transistor is coupled to a second output,
a first switch coupled to a source of the first transistor and a source of the second transistor, and
a first current source coupled to the switch and a first supply voltage;
a plurality of second branches, wherein each of the second branches includes:
a third transistor receiving a third signal at its gate, wherein a drain of the third transistor is coupled to the first output,
a fourth transistor receiving a fourth signal at its gate, wherein a drain of the fourth transistor is coupled to the second output,
a second switch coupled to a source of the third transistor and a source of the fourth transistor, and
a second current source coupled to the switch and a first supply voltage;
a first resistance coupled between a second supply voltage and the first output;
and
a second resistance coupled between the second supply voltage and the second output.

11 more elements

Dependencies are inferred from the claim text.

High speed clock and data recovery system

Life of this patent

High speed clock and data recovery system

Life of this patent

Abstract

Claims57