Delay locked loops and methods using ring oscillators
AssigneeSamsung Electronics Co., Ltd.
InventorKyu-hyoun Kim
Life of this patent
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Abstract
Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.
Claims16
A delay locked loop comprising:
- a delay circuit that is configured to generate an output clock signal by delaying an input clock signal according to a voltage of a control signal, the delay circuit comprising an oscillating circuit to which the input clock signal is input;
- a phase detector that is configured to receive the output clock signal as a feedback signal, to detect a phase difference between the input clock signal and the feedback signal, and to output a result of detection;
- a charge pump that is configured to generate a current corresponding to the result of detection;
- and
- a loop filter that is configured to output the control signal as a voltage that corresponds to the current.
A method of locking a clock signal, comprising:
- generating an output clock signal by delaying an input clock signal according to a voltage of a control signal, using an oscillating circuit to which the input clock signal is input;
- detecting a phase difference between the input clock signal and the output clock signal, and outputting a result of detection;
- generating a current corresponding to the result of detection;
- and
- outputting the control signal as a voltage which corresponds to the generated current.
A delay locked loop comprising:
- a ring oscillator including a plurality of serially connected inverters and a feedback path around the plurality of serially connected inverters, the ring oscillator being configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator;
- and
- a phase-responsive circuit that is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal.
Dependencies are inferred from the claim text.