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US 2006/0076991 A1Published application
Low power high frequency phase detector
AssigneeInternational Business Machines Corporation
InventorsSeung-Moon Yoo, Hung Ngo
Life of this patent
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Abstract
A phase detector employs a modified logic gate in conjunction with a set/reset latch to make a phase detector that generates control outputs for use in increasing and decreasing the delay in a delay circuit in the path of a feedback clock generated by delaying a reference clock. The delay circuit provides a controllable delay from less than to greater than one clock cycle of the reference clock. The phase detector generates an up control (UP) signal for increasing delay when the feedback clock leads the reference clock and a down control (DN) signal for decreasing delay when the feedback clock lags the reference clock. The UP signal and DN signal are updated each clock cycle when the leading clock edge makes a transition.
Claims33
A phase detector generating first and second control signals in response to a phase difference between a first clock and a second clock comprising:
- a latch having a set input, a reset input, a first latch output generating the first control signal, and a second latch output generating the second control signal;
- a first modified logic gate (MLG) having first, second, and third logic inputs, and a first logic output generating a logic one in response to a first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to a second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the first MLG is coupled to the second clock, the second logic input of the first MLG is coupled to the first clock, and the first logic output is coupled to the set input;
- and
- a second MLG having first, second, and third logic inputs and a second logic output generating a logic one in response to the first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to the second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the second MLG is coupled to the first clock, the second logic input of the second MLG is coupled to the second clock, the third logic input of the second MLG is coupled to the first logic output, and the second logic output is coupled to the reset input and the third logic input of the first MLG.
1 more element
A delay locked loop for phase aligning a first clock and a second clock comprising:
- a voltage variable delay circuit having a delay variable in the range from one half a clock cycle of the first clock and greater than one clock cycle of the first clock in response to a control voltage;
- a voltage generator that generates the control voltage as an increasing voltage in response to a first logic state of a first control signal and a decreasing voltage in response to the first logic state of a second control signal;
- and
- a phase detector generating the first and second control signals in response to a phase difference between the first clock and the second clock, the phase detector having a latch with a set input, a reset input, a first latch output generating the first control signal, and a second latch output generating the second control signal, a first modified logic gate (MLG) having first, second, and third logic inputs, and a first logic output generating a logic one in response to a first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to a second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the first MLG is coupled to the second clock, the second logic input of the first MLG is coupled to the first clock, and the first logic output is coupled to the set input, and a second MLG having first, second, and third logic inputs and a second logic output generating a logic one in response to the first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to the second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the second MLG is coupled to the first clock, the second logic input of the second MLG is coupled to the second clock, the third logic input of the second MLG is coupled to the first logic output, and the second logic output is coupled to the reset input and the third logic input of the first MLG.
1 more element
A data processing system comprising:
- a central processing unit (CPU) as one or more integrated circuits having a second clock locally generated from a distributed first clock using a delay locked loop for phase aligning the first clock and the second clock, the delay locked loop having a voltage variable delay circuit having a delay, variable in the range, from one half a clock cycle of the first clock to greater than one clock cycle of the first clock in response to a control voltage, a voltage generator that generates the control voltage as an increasing voltage in response to a first logic state of a first control signal and a decreasing voltage in response to the first logic state of a second control signal, and a phase detector generating the first and second control signals in response to a phase difference between the first clock and the second clock, the phase detector having a latch with a set input, a reset input, a first latch output generating the first control signal, and a second latch output generating the second control signal, a first modified logic gate (MLG) having first, second, and third logic inputs, and a first logic output generating a logic one in response to a first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to a second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the first MLG is coupled to the second clock, the second logic input of the first MLG is coupled to the first clock, and the first logic output is coupled to the set input, and a second MLG having first, second, and third logic inputs and a second logic output generating a logic one in response to the first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to the second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the second MLG is coupled to the first clock, the second logic input of the second MLG is coupled to the second clock, the third logic input of the second MLG is coupled to the first logic output, and the second logic output is coupled to the reset input and the third logic input of the first MLG.
Dependencies are inferred from the claim text.