Balanced debounce circuit with noise filter for digital system
AssigneeBroadcom Corporation
InventorsRobin Lu, Yan Zhang
Life of this patent
Estimating the term…
Abstract
A circuit and method for debouncing an electrical signal are disclosed. A representative embodiment of the present invention may be set to remove (i.e., filter) noise or glitches in the low and high portions of an input signal, where the width of the noise or glitches while in the high or low state may be set using a programming interface. The filtering is done in a manner that results in a clean, debounced output signal having a low portion approximately equal to the low portion of the input signal, and a high portion approximately equal to the high portion of the input signal. Noise or glitches of less than programmable high or low glitch widths are filtered from the input signal and do not appear in the output signal.
Claims31
A circuit for debouncing an input signal having at least a first state and a second state, the circuit comprising:
- a first counter that responds to a clock signal while the input signal is in the first state, and that is maintained at a first reset value while the input signal is in the second state, the first counter producing an output;
- a second counter that responds to the clock signal while the input signal is in the second state, and that is maintained at a second reset value while the input signal is in the first state, the second counter producing an output;
- a first comparator that produces an output indicating whether a match of the first output to a first predetermined value exists;
- a second comparator that produces an output indicating whether a match of the second output to a second predetermined value exists;
- and
- a latch having an output that is set to the first state when a match of the first output to a first predetermined value exists, and that is set to the second state when a match of the second output to a second predetermined value exists.
A debouncing circuit for filtering an input signal having at least a first state and a second state, the circuit comprising:
- a first timing circuit for measuring a first time period while the input signal is in the first state, wherein the first timing circuit is responsive to a clock input while the input signal is in the first state, and wherein the first timing circuit is held at a first reset value while the input signal is in the second state;
- a second timing circuit for measuring a second time period while the input signal is in the second state, wherein the second timing circuit is responsive to the clock input while the input signal is in the second state, and wherein the second timing circuit is held at a second reset value while the input signal is in the first state;
- and
- a deglitching circuit that produces, in response to the clock input, an output signal taking the first state when the first time period is at least a first predetermined value, and taking the second state when the second time period is at least a second predetermined value.
A method of debouncing an input signal having at least a first state and a second state to produce an output signal, the method comprising:
- measuring a first time period and resetting a second time period, while the input signal is in the first state;
- measuring the second time period and resetting the first time period, while the input signal is in the second state;
- setting the output signal to the first state, if the first time period is at least a first predetermined time period;
- and
- setting the output signal to the second state, if the second time period is at least a second predetermined time period.
A machine-readable storage, having stored thereon a computer program having a plurality of code sections for debouncing an input signal having at least a first state and a second state to produce an output signal, the code sections executable by a machine for causing the machine to perform the operations comprising:
- measuring a first time period and resetting a second time period, while the input signal is in the first state;
- measuring the second time period and resetting the first time period, while the input signal is in the second state;
- setting the output signal to the first state, if the first time period is at least a first predetermined time period;
- and
- setting the output signal to the second state, if the second time period is at least a second predetermined time.
A digital circuit for debouncing an input signal having a first state and a second state and producing an output, the circuit disposed entirely within an integrated circuit device and functioning at least to communicate to the output only changes of input signal state occurring at least a predetermined period of time after the most recent previous change of input signal state.
A digital circuit for debouncing an input signal having a first state and a second state, the circuit disposed within an integrated circuit device and functioning at least to produce an output signal having a predetermined minimum period of time between output state transitions without the use of at least one of an resistor and a capacitor for setting the predetermined minimum period of time.
Dependencies are inferred from the claim text.