System and method for accurate negative bias temperature instability characterization
AssigneeTexas Instruments Incorporated
InventorsAnand Krishnan, Srikanth Krishnan, Vijay Reddy, Cathy Chancellor
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Abstract
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
Claims13
A method for characterizing the negative temperature bias instability of a transistor, comprising:
- maintaining a bias voltage at a drain terminal of the transistor during a test period;
- maintaining a stress voltage at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage;
- and
- measuring at least one characteristic of the transistor at periodic intervals during the stress period while maintaining the stress voltage at the gate terminal to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
13-20. (canceled)
Dependencies are inferred from the claim text.