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US 2006/0076691 A1Published application
Chip bond layout for chip carrier for flip chip applications
AssigneeAdvanced Micro Devices, Inc.
InventorsHelmut Prengel, Frank Schneider
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Abstract
A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.
Claims33
A chip carrier for flip chip bond application, comprising:
- a first wiring layer;
- a second wiring layer;
- a plurality of bumps disposed on said first wiring layer;
- a first portion of said plurality of bumps representing peripheral bumps and being routed out by said first wiring layer;
- a second portion of said plurality of bumps representing inner bumps and being routed out by said first and second wiring layers;
- and
- said peripheral bumps defining a contiguous peripheral bump region surrounding said inner bumps.
4 more elements
A system comprising:
- a semiconductor chip comprising a bump layout and the chip being flip chip bonded to a chip carrier, wherein the chip carrier comprises:
- at least a first and a second signal layer;
- a bump layout arranged on said first signal layer, wherein the bump layout comprises:
- peripheral bumps disposed in a peripheral bump region of the chip;
- and
- inner bumps disposed within said peripheral bump region in an inner bump region;
- and
- a via region disposed within said peripheral bump region to dispose at least one via in the via region for each inner bump.
5 more elements
Dependencies are inferred from the claim text.