Post passivation interconnection schemes on top of the IC chips
AssigneeMegic Corporation
InventorsMou-Shiung Lin, Jin-Yuan Lee
Life of this patent
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Abstract
A new method is provided for the-creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Claims22
1-93. (canceled)
A method for fabricating an electronic component comprising:
- providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein depositing said metallization structure comprises a damascene process;
- and
- depositing a passive device over said passivation layer.
A method for fabricating an electronic component comprising:
- providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a polymer layer over said metallization structure, wherein depositing said metallization structure comprises a damascene process;
- and
- depositing a passive device over said polymer layer.
A method for fabricating an electronic component comprising:
- providing a substrate, and a metallization structure over said substrate, and an insulating layer over said metallization structure, wherein depositing said metallization structure comprises a damascene process;
- and
- depositing a passive device over said insulating layer.
Dependencies are inferred from the claim text.