Semiconductor device having variable thickness insulating film and method of manufacturing same
AssigneeSamsung Mobile Display Co., Ltd.
InventorTae-Wook Kang
Life of this patent
Estimating the term…
Abstract
Embodiments of a semiconductor device capable of increasing an aperture ratio of an organic electroluminescence display device by decreasing the surface area of a capacitor in the organic electroluminescence display device and a method of manufacturing the semiconductor device are disclosed. By forming a gate insulating film of a gate electrode with a thickness different from that of a dielectric film of a capacitor, the surface area of the capacitor can be decreased without variation in capacitance, thereby increasing the aperture ratio of an organic electroluminescence display device.
Claims33
A semiconductor device comprising:
- a plurality of semiconductor-layer patterns formed on a substrate, which includes a first area and a second area;
- an insulating film formed on substantially the entire surface of the substrate including the semiconductor-layer patterns, wherein the insulating film has a first thickness on a part of the first area and the second area that is less than a second thickness on a central portion of the semiconductor-layer pattern in the first area;
- and
- a plurality of conductive-layer patterns formed on the insulating film so as to cover the central portion of the semiconductor-layer pattern in the first area and the semiconductor-layer pattern in the second area.
A semiconductor device comprising:
- a plurality of semiconductor-layer patterns formed on a substrate, which includes a first area, a second area, and a third area;
- an insulating film formed on substantially the entire surface of the substrate including the semiconductor-layer patterns, wherein the insulating film has a first thickness on a part of the second area and the third area that is less than a second thickness on the first area and a central portion of the semiconductor-layer pattern in the second area;
- and
- a plurality of conductive-layer patterns formed on the insulating film to cover the central portions of the semiconductor-layer patterns in the first and second areas and the semiconductor-layer pattern in the third area.
A method of manufacturing a semiconductor device, the method comprising:
- forming a plurality of semiconductor-layer patterns on a substrate which includes a first area and a second area;
- forming an insulating film on the surface of the substrate including the semiconductor-layer patterns;
- forming a photo-resist pattern on the insulating film to cover a central portion of the semiconductor-layer pattern in the first area;
- implanting impurity ions into the semiconductor-layer patterns of the first and second areas using the photo-resist pattern as an ion implanting mask;
- removing, by a predetermined thickness, the insulating film exposed in the first and second areas using the photo-resist pattern as an etching mask;
- removing the photo-resist pattern;
- and
- forming conductive-layer patterns on the central portion of the semiconductor-layer pattern in the first area and on the semiconductor-layer pattern in the second area.
A method of manufacturing a semiconductor device, the method comprising:
- forming a plurality of semiconductor-layer patterns on a substrate which includes a first area, a second area, and a third area;
- forming an insulating film on the surface of the substrate including the semiconductor-layer patterns;
- forming a photo-resist pattern on the insulating film to cover central portions of the semiconductor-layer patterns in the first and second areas;
- implanting first conductive-type impurity ions with a high concentration into the semiconductor-layer patterns of the second and third areas using the photo-resist pattern as an ion implanting mask;
- removing, by a predetermined thickness, the insulating film exposed in the second and third areas using the photo-resist pattern as an etching mask;
- removing the photo-resist pattern;
- forming conductive-layer patterns on the central portions of the semiconductor-layer patterns in the first and second areas and on the semiconductor-layer pattern in the third area;
- implanting the first conductive-type impurity ions with a low concentration into the semiconductor-layer pattern in the second area;
- and
- implanting second conductive-type impurity ions with a high concentration into the semiconductor-layer pattern in the first area.
Dependencies are inferred from the claim text.